A web site with lots of books

I've been using this website for a long time. It shares many e-books mostly written in English. Some books are hardly found on the internet. I even got one excellent handbook published this year about EDA on it. Here is the link, Pdfchm. Not surprisingly, you have to sign up to proceed. :)

IBM and Mentor Graphics to Develop 22nm Computational Lithography Solution for the Integrated Circuit Industry

Today, the news that Mentor and IBM jointly develop the technology for 22-nm process node caught my eyes. I remember not long ago, Aart de Geus, CEO of Synopsys, created a new term econology in an interview with EE-times. He told us that the innovative technology may take 3 years to develop and another 3 years to get matured. The money invested might be millions. He don't think the investors feel happy about this (neither do I). He further explained that no single company in the world has enough resource to develop new technology alone. The jointly development is the future way of business model. By combining the specific knowledge and resources of several organizations, it would be much easier for them to explore new world.

I totally agree what he said. As a developer at EDA industry, I know that I don't really understand what troubles the different process technology would bring us. The best way to figure it out is to sit down and work with experts from foundry.

Nanoroute Patent

If you are interested in looking at the Nanoroute patent and seeing what it's like, go to this website. The patent has just been granted earlier this year after a four-year approval period.

I read the patent a few years ago but found it was very "fuzzy" in that they didn't disclose anything important in the patent. Now that it has been approved, it will make it even more difficult for Astro or any other router to catch up with Nanoroute because they can't use the "graph-based" routing method that has been patented by Cadence.

Important EDA-related Conferences

DAC - Design Automation Conference
ICCAD - Int'l Conference on Computer-Aided Design
DATE – Design Automation and Test in Europe
ASPDAC - Asia and South Pacific Design Automation Conference
ISPD - Int'l Symposium on Physical Design
ISOCC - Int'l SoC Design Conference
TAU - Int'l Workshop on Timing Issues in the Specification and Synthesis of Digital Systems
GLSVLSI - Great Lakes Symposium on VLSI
CICC - Custom Integrated Circuits Conference
ISQED – International Symposium on Quality Electronic Design
ISLPED - International Symposium on Low Power Electronics and Design
ISCAS – International Symposium on Circuit and System

高通助陣 台積45奈米明年上路

中時電子報更新日期:2006/09/11 04:09 記者:　涂志豪台北報導

手機晶片大廠高通（Qualcomm）表示，已經開始著手四五奈米先進製程研發，雖然仍有許多材料上或製程上的問題有待解決，不過整個進展速度仍十分順利，預計明年下旬就可開始與台積電等晶圓代工夥伴進入試產階段，十分符合台積電宣稱明年下半年走入四五奈米世代的預估。相較於台積電對四五奈米世代的積極攻城掠地，聯電外傳亦與德儀合作，明年底前就會跨足四五奈米市場。

雖然奈米製程的資本支出需求愈來愈大，不過隨著一九三奈米波長的浸潤式顯影製程（immersion lithography）設備已可支援至三二奈米世代，在關鍵設備不需大幅替換情況下，晶圓代工廠在六五奈米製程開始進入接單量產階段後，也延續摩爾定律（Moore's Law）原則，開始著手布局下一世代四五奈米製程。

以台積電為例，目前四五奈米製程的浸潤式顯影技術已有所突破，根據公司方面日前法說會中提供的資料來看，台積電試產的SRAM最佳缺陷密度為零，代表四五奈米已是可行之路。而台積電九○奈米及六五奈米大客戶高通，表示已與台積電等晶圓代工廠合作，開始進行四五奈米的研發，明年下旬就可試產，顯示台積電應可在客戶的力挺下，明年順利走入四五奈米世代。

至於今年亦投入上百億元資金擴充高階奈米製程浸潤式顯影設備的聯電，雖然還沒公布四五奈米技術藍圖及生產時間表，但是外傳聯電已開始與大客戶之一的德儀合作，為明年底或後年初，以四五奈米製程進行試產進行布局。

全球第三大晶圓代工廠特許半導體（Chartered），因與IBM、三星、英飛凌等共同合作研發四五奈米技術有成，已經快速拉近與台積電、聯電間的技術落差時間，由於在IBM及大客戶之一的超微力挺下，六五奈米已有不錯成績，明年底開始投入四五奈米試產應該不會是太難的事。

市場分析師認為，目前九○奈米激烈的殺價競爭態勢，除了延續到年底的六五奈米市場上外，○八年上旬四五奈米市場競爭亦會十分激烈，尤其晶圓代工廠間四五奈米試產時程相近，包括三星、東芝等IDM廠的四五奈米研發亦有一定成果，並以此投入晶圓代工市場爭取訂單，殺價競爭可能會比現在更「血腥」。

The new EDA industry

See here

深次微米SoC挑戰 EDA無法順利銜接製程的推進

內容

The history of EDA industry

There is a good article in EDACafe talking about the history of EDA industry.
Link

TSMC Reference Flow 7.0

Mentor DFM flow

Automatic Environment For DRC Rule File Development And QA

The process of verifying DRC rule files is becoming more complicated as technologies of 90 nm and smaller are reached. A typical DRC rule file for the 90 nm technology node has around 1000 different rules that need to be verified using dedicated layout test patterns for each rule category. These test patterns are generated manually or using semi-automatic scripts that need to be called by the QA engineer with special parameters and are difficult to use and maintain. This job is extremely tedious and time consuming considering that thousands of shapes need to be created. In addition, the created shapes need to ensure coverage by considering as many cases as possible of the pass and fail situations of each DRC rule. Moreover, the results of the DRC run on test patterns need to be analyzed to ensure that the rule file developer has properly represented the design rule. Meeting these challenges calls for improved methodologies that make effective use of automation to enhance quality, reduce development cycle time, and improve productivity.

A key to effective automation is providing a generic rule format that enables description of design rules by process engineers in a standard and consistent way. Doing so will not only address the above problems but it will eliminate communication errors between process engineers and rule developers. It can also support further enhancements such as automatically generating the entire rule file.

One way to construct a generic rule format is based on special keywords. Each keyword can target one rule category (i.e., spacing, width …) and additional arguments should follow the keyword to give further insight about the rule like the layers involved, constraints and so on. There should be room as well for more advanced arguments to further describe complicated situations like orientation, projection, singularity, connectivity, etc. In general keywords should be generic and their number should be kept to a minimum. On the other hand, they should be capable of representing the design manual entirely.

Considering test pattern generation, the methodology should address important issues like rule coverage, layer mapping and layer derivation. It should provide a database of test patterns that are technology node independent. More importantly, the database must include test patterns that cover all violation scenarios considered by the DRC rules. The key to test pattern coverage is experience and continuous improvements, so the database must facilitate capturing new test pattern requirements that cover new or updated scenarios.

Considering rule file generation, a template has to be created with controllable switches to account for optional arguments in the generic rule format. It should consider also the best practices of the targeted DRC tool to provide optimized, high quality rules.

Mentor Consulting has devised a methodology that efficiently addresses these issues and challenges. A possible flow representing this methodology is shown in Figure 1. This methodology provides a means for automating DRC test pattern and rule file generation and QA reporting. This methodology not only saves time, improves productivity, ensures consistent and accurate QA, but it enables continuous improvement of test pattern coverage and rule quality.